This invention relates to the field of design verification, more specifically, to an approach for functional verification of digital designs.
The object of design verification is to ensure that errors are absent from a design. Deep sub-micron integrated circuit (IC) manufacturing technology is enabling IC designers to put millions of transistors on a single IC. Following Moore""s law, design complexity is doubling every 12-18 months, which causes design verification complexity to increase at an exponential rate. Because of their complexity, manual analysis of these IC designs becomes quite cumbersome. In addition, competitive pressures are putting increased demands on reducing time to market. The combination of these forces has caused an ever worsening verification crisis.
Today""s design flow starts with a specification for the design. The designer implements the design in a language model, typically Hardware Description Language (HDL). This model is typically verified to discover incorrect input/output (IO) behavior via a stimulus in expected results out paradigm at the top level of the design.
By far the most popular method of functional verification today, simulation-based functional verification, is widely used within the digital design industry as a method for finding defects within designs. Products are available in the market to support simulation-based verification methodologies. A wide variety of products provide for a set of design verification checks to allow conclusions to be drawn about the hardware design. The checks may be used to provide error reporting. However, with integrated circuits having millions of transistors, and more, designers are being inundated with error messages in a disorganized fashion that is very time consuming to sort through, as illustrated by FIG. 1.
Another problem with prior products is that they may not provide an exhaustive analysis of a design. Moreover, these products produce large amounts of noise, or data that does not provide meaningful information about the main errors within a design. For example, a check may be dependent upon a set of other checks if it is impossible to violate the first without violating at least one or more checks from the set. Prior checking methods do not consider dependency relationships among the comprehensive set of design verification checks to be determined. As such, redundant failures due to multiple violations resulting from a common design error may be reported. In this manner, verification of design errors is made more inefficient because designers are inundated with redundant and cumulative information.
The present invention pertains to a method and apparatus for characterizing information about a design attribute. In one embodiment, the method may include determining a relationship between attributes of hardware design and performing an analysis for the existence of a violation of the attributes. The method may also include reporting the results of the analysis based on the relationship.
In one embodiment, the information may be characterized by determining dependency relationships among the attributes, with each of the attributes representing a condition that, if violated, indicates that the design does not operate correctly. In one particular embodiment, an attribute may represent a condition that must hold true in order for the hardware design to operate in accordance with an intended flow of logical signals in the hardware design.
In one embodiment, the reporting may include identifying the violations of the plurality of attributes with a particular priority such as a primary and a secondary violation. The reporting may also include presenting only the primary violations. In an alternative embodiment, both the primary and the secondary violations may be presented with the primary violations being more prominently presented.